QC-BiCMOS (Quasi Complementary BiCMOS) circuits provide good performance for sub-micron VLSI logic gates operating in the 3.3 volt power supply region. A recognized problem with QC-BiCMOS, however, is the manner in which pull down bipolar transistors are turned off. Any practical scheme used to turn off the pull down transistor(s) must ensure that the pull down transistor(s) receive maximum base drive until the pull down transition is completed. The turn off scheme must also provide a means for discharging the shallow saturation a pull down transistor attains during the pull down transition. The problem is one of ensuring the shallow saturation is removed as soon as possible without diverting the base drive needed for a fast pull down transition.
FIG. 1 is a schematic diagram of a prior art QC-BiCMOS circuit, shown generally at 10. When node 12 is at a logic low voltage, P-channel transistor 14 provides base drive to pull down bipolar transistor 16. Transistor 14 provides base drive to transistor 16 until the collector voltage drops below the threshold of transistor 14. Enough carriers are delivered to the base node 18 to drive transistor 16 into shallow saturation forcing the collector voltage to become less than the base voltage. Some shallow saturation is desired to obtain a fast pull down transition below a Vbe. With transistor 14 turned off, base node 18 becomes a high impedance node with the base of transistor 16 being the sole discharge path. It is necessary to remove the shallow saturation once the output pull down transition is achieved. If the shallow saturation is not removed the next pull up transition could cause a transistor 20 & 16 short circuit condition when transistor 20 forces transistor 16 out of shallow saturation. The base node voltage, however must not be discharged until the output pull down transition is complete.
The inverter of transistors 22 & 24 attempts to remove the shallow saturation. The inverter of transistor 22 & 24 drives base node clamping transistor 26. When transistor 26 turns on, node 18 is discharged to ground potential, pulling transistor 16 out of shallow saturation. But, this attempt at clamping the base creates a problem. The inverter (transistors 22 & 24) must be carefully scaled to ensure the clamping signal does not arrive too early. If the clamping signal arrives early, transistor 26 will divert current desired for transistor 16 base drive. Contrariwise, if the clamping signal is delayed too much and does not arrive before the next output pull up transition, a short circuit current condition through transistors 20 and 16 may occur. Transistor 16 will still be in shallow saturation resulting in transistor 16 being in an ON state while transistor 20 is providing pull up drive. As a result, providing a properly timed clamp signal that satisfies all possible output loading conditions with this method is difficult.
The problem associated with this method of clamping the base node is shown in the SPICE simulation waveforms of FIG. 2. As can be seen, the base voltage 30 of transistor 16 remains larger than the collector voltage 28 from about 1.0 ns until the base clamp signal arrives. The base clamp signal arrival is seen when the waveform of transistor 16 goes negative (around 1.5 ns) and starts to reduce the voltage at the base of transistor 16. The shaded area denotes the time that the base voltage 30 remains larger than the collector voltage 28 indicating shallow saturation. The output 32 of FIG. 1 is restored to a zero volt potential when the output is a logic low level through ON transistors 34 and 36. When output 32 is a logic high, the output voltage is restored to Vcc potential through ON transistors 38 and 40. Inverters made of transistors 38 & 42 and 36 & 44 are scaled such that smallest turn on times for transistors 20 and 16 are provided while also satisfying the requirement that both transistors 20 and 16 do not both remain transiently on at the same time allowing a rail to rail short circuit condition to exist.